WO2001069411A3 - Memory interface and method of interfacing between functional entities - Google Patents
Memory interface and method of interfacing between functional entities Download PDFInfo
- Publication number
- WO2001069411A3 WO2001069411A3 PCT/US2001/007197 US0107197W WO0169411A3 WO 2001069411 A3 WO2001069411 A3 WO 2001069411A3 US 0107197 W US0107197 W US 0107197W WO 0169411 A3 WO0169411 A3 WO 0169411A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- memory
- interface
- function
- ports
- interfacing
- Prior art date
Links
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Abstract
A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2001243463A AU2001243463A1 (en) | 2000-03-10 | 2001-03-07 | Memory interface and method of interfacing between functional entities |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US18854600P | 2000-03-10 | 2000-03-10 | |
US60/188,546 | 2000-03-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001069411A2 WO2001069411A2 (en) | 2001-09-20 |
WO2001069411A3 true WO2001069411A3 (en) | 2003-04-17 |
Family
ID=22693607
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/007197 WO2001069411A2 (en) | 2000-03-10 | 2001-03-07 | Memory interface and method of interfacing between functional entities |
Country Status (3)
Country | Link |
---|---|
US (5) | US6988154B2 (en) |
AU (1) | AU2001243463A1 (en) |
WO (1) | WO2001069411A2 (en) |
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Also Published As
Publication number | Publication date |
---|---|
US8959269B2 (en) | 2015-02-17 |
US20150154143A1 (en) | 2015-06-04 |
WO2001069411A2 (en) | 2001-09-20 |
US9418042B2 (en) | 2016-08-16 |
US20090055565A1 (en) | 2009-02-26 |
AU2001243463A1 (en) | 2001-09-24 |
US20060174081A1 (en) | 2006-08-03 |
US8688879B2 (en) | 2014-04-01 |
US20030009612A1 (en) | 2003-01-09 |
US20140281114A1 (en) | 2014-09-18 |
US6988154B2 (en) | 2006-01-17 |
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