WO2002006960A1 - Memory access method and apparatus - Google Patents

Memory access method and apparatus Download PDF

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Publication number
WO2002006960A1
WO2002006960A1 PCT/US2001/021511 US0121511W WO0206960A1 WO 2002006960 A1 WO2002006960 A1 WO 2002006960A1 US 0121511 W US0121511 W US 0121511W WO 0206960 A1 WO0206960 A1 WO 0206960A1
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WIPO (PCT)
Prior art keywords
memory
sub
package
address
unit
Prior art date
Application number
PCT/US2001/021511
Other languages
French (fr)
Inventor
Han-Ping Chen
Original Assignee
Chen Han Ping
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chen Han Ping filed Critical Chen Han Ping
Priority to AU2001273258A priority Critical patent/AU2001273258A1/en
Publication of WO2002006960A1 publication Critical patent/WO2002006960A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications

Definitions

  • This invention relates to semiconductor memory devices, memory chips, memory modules, memory controllers, and the handling of defective memory components.
  • a semiconductor memory wafer Due to the yield limitation of semiconductor fabrication process, a semiconductor memory wafer usually contains defective memory devices. As the cell density of the semiconductor device increases, it is becoming harder to achieve high production yield.
  • certain repairing process may be used to replace defective rows or columns in the memory cell array.
  • Some memory devices remain defective at the semiconductor die level after the fabrication process.
  • This invention proposes a method and apparatus to efficiently utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a functional package.
  • This invention provides a method that maximizes the usage of non- defective memory data bits in the partially defective memory devices.
  • the present invention provides a method that simplifies the production and process of memory chips or modules.
  • FIG. 1 is a diagram of a prior art memory chip.
  • FIG. 2 is a diagram of a prior art memory module.
  • FIG. 3 shows a preferred embodiment of the present invention for a memory assembly.
  • FIG.4 shows a preferred embodiment of the present invention for a memory access controller.
  • FIG. 5 shows a preferred embodiment of an address generator logic unit.
  • FIG. 6 shows a preferred embodiment of a basic logic unit stage.
  • FIG. 7 shows a preferred embodiment of a memory selection control unit.
  • FIG. 8 shows another preferred embodiment of the present invention for a memory assembly.
  • FIG. 9 shows another preferred embodiment of a memory access controller.
  • FIG. 10 shows a preferred embodiment of an address generator logic unit.
  • FIG. 11 shows a different preferred embodiment of an address generator unit.
  • FIG. 12 shows a different preferred embodiment of a basic logic unit stage.
  • FIG. 13 shows another preferred embodiment of an address generator unit.
  • FIG. 14 shows another preferred embodiment of a basic logic unit stage.
  • FIG. 15 shows another preferred embodiment of an address generator logic unit.
  • FIG. 16 shows a preferred embodiment of the present invention for a memory module assembly.
  • FIG. 17 shows a preferred embodiment of a memory access controller.
  • FIG. 18 shows a different preferred embodiment of the present invention for a memory module assembly.
  • FIG. 19 shows a different preferred embodiment of a memory access controller.
  • FIG. 20 shows another different preferred embodiment of the present invention for a memory module assembly.
  • FIG. 1 is a diagram of a prior art memory chip.
  • the memory device 101 contains device data port 102, a device address unit 103, a device control unit 104, and a memory cell array 105.
  • the device data port 102 is connected to the chip data bus 106.
  • the device address unit 103 is connected to the chip address bus 107.
  • the device control unit 104 is connected to the chip control bus 108.
  • FIG. 2 is a diagram of a prior art memory module.
  • the memory module 201 receives address-control signals on a memory address-control bus 202.
  • the address-control signals select memory data from the memory device 203.
  • the selected memory data is placed on a device data port 204.
  • the memory data further passes through a connection element 205 to reach the memory data bus 206.
  • the combination of a memory device 203 and a connection element 205 constitutes a memory unit.
  • This memory module contains a total of eight memory units.
  • FIG. 3 shows a preferred embodiment of the present invention for a memory assembly.
  • the primary memory unit 301 is connected to the memory address bus 302, memory control bus 303, and memory data bus 304.
  • the memory cell array is divided into 16 primary memory blocks.
  • a primary memory unit may be divided into any number of blocks. Each block contains a number of memory cells.
  • Primary memory unit 301 contains defective memory cells within memory blocks 305, 306, 307, and 308. The primary block numbers for these defective blocks are hexadecimal numbers 02h, 04h, 07h, and 08h.
  • the standby memory unit 309 provides alternative memory storage to replace the defective areas in the primary memory unit 301.
  • the standby memory unit may contain any number of standby memory blocks. In this embodiment, the standby memory unit 309 contains 4 standby memory blocks.
  • the memory access controller 310 performs the control functions for the replacement operation.
  • the memory address decoder 311 decodes the selected memory address bits into 16 primary block selection lines.
  • the memory status unit 312 specifies the status of the 16 primary memory blocks.
  • the memory selection control unit 313 determines whether to select the primary memory unit or the standby memory unit according to the decoded primary block selection lines and the memory status signals.
  • the memory address generator logic unit 314 generates the appropriate standby memory address for the standby memory unit according to the memory status signals.
  • FIG. 4 shows a preferred embodiment of a memory access controller for the memory assembly in FIG. 3.
  • memory address decoder 404 decodes selected memory address bits 402.
  • the memory status unit 405 specifies the status of the primary memory blocks in the primary memory unit.
  • the memory selection control unit 406 receives control signals from the memory control bus 403 and determines whether to select the primary memory unit or the standby memory unit according to the decoded primary block selection signals and the primary memory status signals.
  • the memory address generator logic unit 407 generates the appropriate standby memory address 408 for the selected memory block according to the memory status signals.
  • FIG. 5 shows a preferred embodiment of an address generator logic unit for the memory assembly in FIG. 3.
  • the memory status unit 501 there are 16 status bits, one bit for each primary block.
  • a functional block is marked with a 0 in the corresponding status entry.
  • a defective block is marked with a 1 in the corresponding status entry.
  • the address generator logic unit contains 16 basic logic unit stages, one for each primary block status bit.
  • the basic logic unit 502 receives a status bit 503 from the memory status unit and an input location number 504 from the previous stage.
  • a logic unit performs a set of basic logic functions to generate an output location number 506 to the next logic stage.
  • the logic unit sends the input location number to the standby memory address output port 507.
  • the basic logic unit performs a binary increment operation. It receives an input location number from the previous stage. The corresponding status bit input serves as a carry-in bit to the least significant bit (LSB). If the carry-in bit is a zero, the logic unit sends the input location number to the next stage as the output location number. If the carry-in bit is a one, the logic unit increments the input location number by 1 and sends it to the next stage as the output location number.
  • LSB least significant bit
  • the first logic unit receives the hexadecimal value OOh from the starting address setting 505 as the input location number.
  • the input-output numbers are marked for each subsequent logic unit as illustrated.
  • the generated memory address outputs for the defective primary memory blocks 02h, 04h, 07h, and 08h are shown as OOh, Olh, 02h, and 03h respectively.
  • the corresponding memory address output number is sent to the standby memory unit to specify the appropriate replacement memory blocks.
  • the defective memory block number 02h is replaced with standby memory block OOh.
  • the defective memory block number 04h is replaced with standby memory block Olh.
  • the defective memory block number 07h is replaced with standby memory block 02h.
  • the defective memory block number 08h is replaced with standby memory block 03h.
  • the location number output of the last logic stage 508 in this case is 04h, which is the next available location number if any remaining.
  • FIG. 6 shows a preferred embodiment of a basic logic unit stage in the memory address generator logic unit.
  • the basic logic unit 601 contains a 4-bit increment logic unit stage.
  • the primary memory block status bit 602 serves as a carry-in bit. When the carry-in bit is 0, the input relocation number 603 passes through unchanged to the output relocation number port 604. When the carry-in bit is 1, the input relocation number 603 is incremented by 1 and then sent to the output relocation number port 604.
  • the basic logic unit stage When the corresponding primary memory block is selected by the selection signal 605, the basic logic unit stage sends the input relocation number 603 through the connection unit 606 to the standby memory address output port 607.
  • FIG. 7 shows a preferred embodiment of a memory address decoder and a memory selection control unit.
  • the memory address decoder 701 decodes the memory address bits 702 into 16 primary block selection lines 703.
  • the memory selection control unit 704 accepts memory block selection lines 703 and memory status signals 705.
  • the selected memory block is determined to be defective.
  • the corresponding defective flag 706 is set to 1.
  • the standby memory unit selection signal 707 is set to 1 and the primary memory selection signal 708 is set to O.
  • FIG. 8 shows another preferred embodiment of the present invention for a memory assembly.
  • the memory unit 801 is connected to the memory address bus 802, memory control bus 803, and memory data bus 804.
  • the memory cell array is divided into 16 memory blocks.
  • Memory unit 801 contains defective memory cells within memory blocks 805, 806, 807, and 808.
  • the block numbers for these defective blocks are 02h, 04h, 07h, and 08h.
  • the highest 4 memory blocks are allocated as replacement blocks. These 4 memory blocks are tested to be functional before placed into service.
  • the memory access controller 809 performs the control functions for the replacement operation.
  • the memory address decoder 810 decodes the selected memory address bits into 16 memory block selection lines.
  • the memory status unit 811 specifies the status of the 16 memory blocks.
  • the memory address generator logic unit 812 generates the appropriate replacement memory address for the replacement memory blocks according to the memory status signals.
  • the memory selection control unit 813 determines whether to select the original memory address or the replacement memory address according to the decoded block selection lines and the memory status signals.
  • the memory address selector 814 performs the final address selection.
  • FIG. 9 shows a preferred embodiment of a memory access controller for the memory assembly in FIG. 8.
  • memory address decoder 903 decodes selected memory address bits 902.
  • the memory status unit 904 specifies the status of the memory blocks in the memory unit.
  • the memory address generator logic unit 905 generates the appropriate replacement memory address 906 for the selected memory block according to the memory status signals.
  • the memory selection control unit 907 determines whether to select the original memory address or the replacement memory address according to the decoded block selection signals and the memory status signals.
  • Memory address selector 908 performs the final address selection to generate a memory block address 909.
  • FIG. 10 shows a preferred embodiment of an address generator logic unit for the memory assembly in FIG. 8.
  • the operation of this diagram is similar to FIG. 5. The only difference is that the input location number of the first logic stage is set to hexadecimal value OCh, which is the starting block number of the 4 replacement memory blocks.
  • the memory status unit 1001 contains the status bits of the 16 memory blocks.
  • the address generator logic block contains 16 basic logic unit stages.
  • the basic logic unit 1002 receives a status bit 1003 from the memory status unit and an input location number 1004 from the previous stage.
  • a logic unit performs a set of basic logic functions to generate am output location number 1006 to the next logic stage. When the corresponding block is selected, the logic unit sends the input location number to the replacement memory address output port 1007.
  • the basic logic unit performs a binary increment operation. It receives an input location number from the previous stage. The corresponding status bit input serves as a carry-in bit to the least significant bit (LSB). If the carry-in bit is a zero, the logic unit sends the input location number to the next stage as the output location number. If the carry-in bit is a one, the logic unit increments the input location number by 1 and sends it to the next stage as the output location number.
  • LSB least significant bit
  • the first logic unit receives the hexadecimal value OCh from the starting address setting 1005 as the input location number.
  • the input-output numbers are marked for each subsequent logic unit as illustrated.
  • the generated memory address outputs for the defective memory blocks 02h, 04h, 07h, and 08h are shown as OCh, ODh, OEh, and OFh respectively. These replacement memory addresses are used instead of the original memory address for the defective memory block locations.
  • FIG. 11 shows a different preferred embodiment of an address generator unit for the memory assembly in FIG. 8. This operation uses a different basic logic unit stage. Instead of performing an increment operation, the basic logic unit stage performs a decrement operation.
  • the memory status unit 1101 contains the status bits of the 16 memory blocks.
  • the location identification logic unit contains 16 basic logic unit stages.
  • the basic logic unit 1102 receives a status bit 1103 from the memory status unit and an input location number 1104 from the previous stage.
  • a logic unit performs a set of basic logic functions to generate an output location number 1106 to the next logic stage. When the corresponding block is selected, the logic unit sends the input location number to the replacement memory address output port 1107.
  • the basic logic unit performs a binary decrement operation. It receives an input location number from the previous stage. The corresponding status bit input serves as a borrow input to the least significant bit (LSB). If the status bit is a zero, the logic unit sends the input location number to the next stage as the output location number. If the status bit is a one, the logic unit decrements the input location number by 1 and sends it to the next stage as the output location number.
  • LSB least significant bit
  • the first logic unit receives the hexadecimal value OFh from the starting address setting 1105 as the input location number.
  • the input-output numbers are marked for each subsequent logic unit as illustrated.
  • the generated location numbers for the defective memory blocks 02h, 04h, 07h, and 08h are shown as OFh, OEh, ODh, and OCh respectively. These replacement memory addresses are used instead of the original memory address for the defective memory block locations.
  • the defective memory block number 02h is replaced with standby memory block OFh.
  • the defective memory block number 04h is replaced with standby memory block OEh.
  • the defective memory block number 07h is replaced with standby memory block ODh.
  • the defective memory block number 08h is replaced with standby memory block OCh.
  • the starting location number input to the first logic stage is always OFh.
  • the location number output of the last logic stage 1108 in this case is OBh, which is the highest logical block address.
  • FIG. 12 shows a preferred embodiment of a basic logic unit stage in the memory address generator logic unit.
  • the basic logic block 1201 contains a 4-bit decrement logic unit stage.
  • the primary memory block status bit 1202 serves as a borrow-in signal.
  • the input relocation number 1203 passes through unchanged to the output relocation number port 1204.
  • the borrow-in is 1, the input relocation number 1203 is decremented by 1 and then sent to the output relocation number port 1204.
  • the basic logic unit stage sends the input relocation number 1203 through the connection unit 1206 to the replacement memory address output port 1207.
  • FIG. 13 shows another preferred embodiment of an address generator logic unit for the memory assembly in FIG. 8.
  • the memory status unit 1301 there are 16 status bits, one bit for each memory block.
  • a functional block is marked with a 0 in the corresponding status entry.
  • a defective block is marked with a 1 in the corresponding status entry.
  • the address generator logic unit contains 16 basic logic unit stages, one for each memory block status bit.
  • the basic logic unit 1302 receives a status bit 1303 from the memory status unit and an input location number 1304 from the previous stage.
  • a logic unit performs a set of basic logic functions to generate an output location number 1306 to the next logic stage.
  • the logic unit also sends the input location number to the logical memory address output port 1307.
  • the basic logic unit performs a binary increment operation. It receives an input location number from the previous stage and a status bit from the status unit.
  • the status bit input is used in a slightly different way. It is first inverted and then used as a carry-in bit to the least significant bit (LSB). If the status bit is a 1, the carry-in bit is 0 and the logic unit sends the input location number to the next stage as the output location number. If the status bit is a 0, the carry-in bit is 1 , the logic unit increments the input location number by 1 and sends it to the next stage as the output location number. In FIG. 13, the first logic unit receives the hexadecimal value OOh as the input location number 1304 from the starting location number 1305. The input- output numbers are marked for each subsequent logic unit as illustrated.
  • LSB least significant bit
  • the generated logical memory location numbers for the functional memory blocks OOh, Olh, 03h, 05h, 06h, 09h, OAh, OBh, OCh, ODh, OEh and OFh are shown as OOh, Olh, 02h, 03h, 04h, 05h, 06h, 07h, 08h, 09h, OAh, and OBh respectively.
  • the location number output of the last logic stage 1308 in this case is OCh, which is the next logical block address after this assembly. It may be used as the starting address number of the next memory controller following this one.
  • a basic logic unit Upon receiving the memory address from the address bus, a basic logic unit compares the input memory address 1309 with the generated logical memory location value 1307 in the comparator 1308. If there is a match, the corresponding location selection line 1310 is set to 1. If there is no match, the corresponding location selection line 1310 is set to 0.
  • the location address encoder 1311 encodes the location selection lines 1310 from all the functional logic units to generate a final memory address output number 1312.
  • FIG. 14 shows a preferred embodiment of a basic logic unit stage for the address generator logic unit in FIG. 13.
  • the logic operation unit 1401 performs a binary increment operation. It receives an input location number 1403 from the previous stage and a status bit 1402 from the status unit.
  • the status bit input is first inverted and then used as a carry-in bit to the least significant bit (LSB). If the status bit is a 1, the carry-in bit is 0 and the logic unit sends the input location number to the next stage as the output location number. If the status bit is a 0, the carry-in bit is 1, the logic unit increments the input location number by 1 and sends it to the next stage as the output location number.
  • LSB least significant bit
  • a logic comparator 1406 Upon receiving the memory address 1405 from the address bus, a logic comparator 1406 compares the input memory address 1405 with the logical memory location value 1403. If there is a match and the status input is a 0 for a functional unit, the corresponding location selection line 1407 is set to 1. If there is no match, the corresponding location selection line 1407 is set to 0.
  • FIG. 15 shows another preferred embodiment of an address generator logic unit for the memory assembly in FIG. 8. The operation is similar to that of FIG. 13 except for a different starting address number.
  • the starting address number 1501 is hexadecimal value 02h.
  • the first logic unit receives the starting location number 1501 as the input location number.
  • the input-output numbers are marked for each subsequent logic unit as illustrated.
  • the generated logical memory address numbers for the functional memory blocks OOh, Olh, 03h, 05h, 06h, 09h, OAh, OBh, OCh, ODh, OEh and OFh are shown as 02h, 03h, 04h, 05h, 06h, 07h, 08h, 09h, OAh, OBh, OCh, and ODh respectively.
  • the location number output of the last logic stage 1502 in this case is OEh, which is the next logical block address after this assembly. It may be used as the starting address number of the next memory controller following this one.
  • this logic unit In responds to memory address inputs 02h, 03h, 04h, 05h, 06h, 07h, 08h, 09h, OAh, OBh, OCh, and ODh, this logic unit will generate the functional block numbers OOh, Olh, 03h, 05h, 06h, 09h, OAh, OBh, OCh, ODh, OEh and OFh respectively. For example, if the memory address input is 07h, the generated address will be 09h.
  • FIG. 16 shows a preferred embodiment of the present invention for a memory module assembly.
  • the first group of memory chips contains four primary memory units 1601.
  • the second group of memory chips contains one standby memory unit 1602.
  • the memory access controller 1603 controls the enabling of these two memory groups.
  • the controller also generates the address for the standby memory unit 1602.
  • the block size of the standby memory unit is smaller than the block size of the primary memory units.
  • the data width of the standby memory unit is also different from the data width of the primary memory units.
  • a standby memory block is assigned to replace a memory area within the shaded region in the primary memory unit in FIG.16.
  • the shaded region is eight times the size of the standby memory block. This introduces some constraints on the replacement process.
  • the standby memory block is designated to replace the marked area 1604 within the shaded region.
  • the selection signal is based on some memory address bits, the physical location of the memory elements, fixed circuit settings, programmable storage cells, or a combination of these parameters.
  • a sub-block address tag may be attached to each memory status indicator to define the sub-block location of the defective area to be replaced.
  • FIG. 17 shows a preferred embodiment of the data routing circuit in a memory access controller for the memory assembly in FIG. 16.
  • the memory data from the standby memory unit is routed to the specified positions for the primary memory units.
  • a decoder logic block 1701 decodes two address lines 1702 into data position control lines 1703. These data position control lines enable the memory data 1704 from a standby memory unit through the data output connecting elements 1705 to the memory data output port 1706.
  • the decoded line 0 controls data bits DO to D7.
  • Decoded line 1 controls data bits D8 to D15.
  • Decoded line 2 controls data bits D16 to D23.
  • Decoded line 3 controls data bits D24 to D31. If the two address lines are 01, the decoded line 1703 will enable the eight-bit data 1704 from the standby memory unit onto data bits D8 to D15 through the connecting element 1705.
  • FIG. 18 shows a different preferred embodiment of the present invention for a memory module assembly.
  • the first group of memory chips contains four primary memory units 1801.
  • the second group of memory chips contains one standby memory unit 1802.
  • the memory access controller 1803 controls the enabling of these two memory groups.
  • the controller also generates the address for the standby memory unit 1802.
  • the block size and data width of the standby memory unit are also different from the block size and data width of the primary memory units.
  • the memory data from the standby memory block is routed to the appropriate memory data positions within a primary block addressing space at the appropriate time to replace the defective areas in the primary memory units.
  • the standby memory block is designated to replace the marked area 1804 within the shaded region.
  • the selection signal is based on some memory address bits, the physical location of the memory elements, fixed circuit settings, programmable storage cells, or a combination of these parameters.
  • a sub-block address tag may be attached to each memory status indicator to define the sub-block location of the defective area to be replaced.
  • the memory access controller 1803 reassigns some of the address bits for the primary memory units.
  • FIG. 19 shows a preferred embodiment of a memory access controller for the memory assembly in FIG. 18.
  • the memory data from the standby memory unit is routed to the specified positions for the primary memory units, similar to the operation in FIG.17.
  • a decoder Upon control signals, a decoder decodes two address lines into four data position control lines. These data position control lines enable the memory data from a standby memory unit through the data output connecting elements to the memory data output port.
  • FIG. 20 shows another different preferred embodiment of the present invention for a memory module assembly. It contains only one group of memory units 2001.
  • the memory access controller 2002 provides an address reassignment mechanism to reassign the address space for the memory units in order to place them in the appropriate memory regions such that the memory module can be used in a degraded manner. In this case, seven of the eight memory regions remain functional after the mapping.

Abstract

A method and apparatus controls the memory access of memory devices (105) in order to utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a fully or partially functional package(101).

Description

MEMORY ACCESS METHOD AND APPARATUS BACKGROUND OF THE INVENTION
This invention relates to semiconductor memory devices, memory chips, memory modules, memory controllers, and the handling of defective memory components.
Due to the yield limitation of semiconductor fabrication process, a semiconductor memory wafer usually contains defective memory devices. As the cell density of the semiconductor device increases, it is becoming harder to achieve high production yield.
During the device fabrication process, certain repairing process may be used to replace defective rows or columns in the memory cell array. However, there is a limit as to the capability of such repairing process. Some memory devices remain defective at the semiconductor die level after the fabrication process.
To repair the memory devices above the die level is a complex issue regarding the feasibility, efficiency, and cost effectiveness.
BRIEF SUMMARY OF THE INVENTION
This invention proposes a method and apparatus to efficiently utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a functional package.
This invention provides a method that maximizes the usage of non- defective memory data bits in the partially defective memory devices.
The present invention provides a method that simplifies the production and process of memory chips or modules.
This invention further provides a method to minimize or eliminate the initialization of the chips or modules. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram of a prior art memory chip. FIG. 2 is a diagram of a prior art memory module.
FIG. 3 shows a preferred embodiment of the present invention for a memory assembly.
FIG.4 shows a preferred embodiment of the present invention for a memory access controller.
FIG. 5 shows a preferred embodiment of an address generator logic unit. FIG. 6 shows a preferred embodiment of a basic logic unit stage. FIG. 7 shows a preferred embodiment of a memory selection control unit. FIG. 8 shows another preferred embodiment of the present invention for a memory assembly. FIG. 9 shows another preferred embodiment of a memory access controller.
FIG. 10 shows a preferred embodiment of an address generator logic unit.
FIG. 11 shows a different preferred embodiment of an address generator unit.
FIG. 12 shows a different preferred embodiment of a basic logic unit stage.
FIG. 13 shows another preferred embodiment of an address generator unit.
FIG. 14 shows another preferred embodiment of a basic logic unit stage.
FIG. 15 shows another preferred embodiment of an address generator logic unit.
FIG. 16 shows a preferred embodiment of the present invention for a memory module assembly.
FIG. 17 shows a preferred embodiment of a memory access controller.
FIG. 18 shows a different preferred embodiment of the present invention for a memory module assembly.
FIG. 19 shows a different preferred embodiment of a memory access controller.
FIG. 20 shows another different preferred embodiment of the present invention for a memory module assembly.
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be illustrated with some preferred embodiments.
FIG. 1 is a diagram of a prior art memory chip. The memory device 101 contains device data port 102, a device address unit 103, a device control unit 104, and a memory cell array 105. The device data port 102 is connected to the chip data bus 106. The device address unit 103 is connected to the chip address bus 107. The device control unit 104 is connected to the chip control bus 108.
FIG. 2 is a diagram of a prior art memory module. The memory module 201 receives address-control signals on a memory address-control bus 202. The address-control signals select memory data from the memory device 203. The selected memory data is placed on a device data port 204. The memory data further passes through a connection element 205 to reach the memory data bus 206. The combination of a memory device 203 and a connection element 205 constitutes a memory unit. This memory module contains a total of eight memory units.
FIG. 3 shows a preferred embodiment of the present invention for a memory assembly. The primary memory unit 301 is connected to the memory address bus 302, memory control bus 303, and memory data bus 304.
In the primary memory unit 301, the memory cell array is divided into 16 primary memory blocks. A primary memory unit may be divided into any number of blocks. Each block contains a number of memory cells. Primary memory unit 301 contains defective memory cells within memory blocks 305, 306, 307, and 308. The primary block numbers for these defective blocks are hexadecimal numbers 02h, 04h, 07h, and 08h.
The standby memory unit 309 provides alternative memory storage to replace the defective areas in the primary memory unit 301. The standby memory unit may contain any number of standby memory blocks. In this embodiment, the standby memory unit 309 contains 4 standby memory blocks.
The memory access controller 310 performs the control functions for the replacement operation. The memory address decoder 311 decodes the selected memory address bits into 16 primary block selection lines. The memory status unit 312 specifies the status of the 16 primary memory blocks.
The memory selection control unit 313 determines whether to select the primary memory unit or the standby memory unit according to the decoded primary block selection lines and the memory status signals.
The memory address generator logic unit 314 generates the appropriate standby memory address for the standby memory unit according to the memory status signals.
FIG. 4 shows a preferred embodiment of a memory access controller for the memory assembly in FIG. 3.
In the memory access controller 401, memory address decoder 404 decodes selected memory address bits 402. The memory status unit 405 specifies the status of the primary memory blocks in the primary memory unit. The memory selection control unit 406 receives control signals from the memory control bus 403 and determines whether to select the primary memory unit or the standby memory unit according to the decoded primary block selection signals and the primary memory status signals.
The memory address generator logic unit 407 generates the appropriate standby memory address 408 for the selected memory block according to the memory status signals.
FIG. 5 shows a preferred embodiment of an address generator logic unit for the memory assembly in FIG. 3. In the memory status unit 501, there are 16 status bits, one bit for each primary block. A functional block is marked with a 0 in the corresponding status entry. A defective block is marked with a 1 in the corresponding status entry.
The address generator logic unit contains 16 basic logic unit stages, one for each primary block status bit. The basic logic unit 502 receives a status bit 503 from the memory status unit and an input location number 504 from the previous stage. A logic unit performs a set of basic logic functions to generate an output location number 506 to the next logic stage. When the corresponding primary block is selected, the logic unit sends the input location number to the standby memory address output port 507.
In this embodiment, the basic logic unit performs a binary increment operation. It receives an input location number from the previous stage. The corresponding status bit input serves as a carry-in bit to the least significant bit (LSB). If the carry-in bit is a zero, the logic unit sends the input location number to the next stage as the output location number. If the carry-in bit is a one, the logic unit increments the input location number by 1 and sends it to the next stage as the output location number.
In FIG. 5, the first logic unit receives the hexadecimal value OOh from the starting address setting 505 as the input location number. The input-output numbers are marked for each subsequent logic unit as illustrated. The generated memory address outputs for the defective primary memory blocks 02h, 04h, 07h, and 08h are shown as OOh, Olh, 02h, and 03h respectively. When a defective primary memory block is selected, the corresponding memory address output number is sent to the standby memory unit to specify the appropriate replacement memory blocks.
The defective memory block number 02h is replaced with standby memory block OOh. The defective memory block number 04h is replaced with standby memory block Olh. The defective memory block number 07h is replaced with standby memory block 02h. The defective memory block number 08h is replaced with standby memory block 03h.
The location number output of the last logic stage 508 in this case is 04h, which is the next available location number if any remaining.
FIG. 6 shows a preferred embodiment of a basic logic unit stage in the memory address generator logic unit. In this embodiment, the basic logic unit 601 contains a 4-bit increment logic unit stage. The primary memory block status bit 602 serves as a carry-in bit. When the carry-in bit is 0, the input relocation number 603 passes through unchanged to the output relocation number port 604. When the carry-in bit is 1, the input relocation number 603 is incremented by 1 and then sent to the output relocation number port 604.
When the corresponding primary memory block is selected by the selection signal 605, the basic logic unit stage sends the input relocation number 603 through the connection unit 606 to the standby memory address output port 607.
FIG. 7 shows a preferred embodiment of a memory address decoder and a memory selection control unit.
The memory address decoder 701 decodes the memory address bits 702 into 16 primary block selection lines 703. The memory selection control unit 704 accepts memory block selection lines 703 and memory status signals 705.
In case a memory block selection line and the corresponding block status bit are both 1, the selected memory block is determined to be defective. The corresponding defective flag 706 is set to 1. As a result, the standby memory unit selection signal 707 is set to 1 and the primary memory selection signal 708 is set to O.
FIG. 8 shows another preferred embodiment of the present invention for a memory assembly. The memory unit 801 is connected to the memory address bus 802, memory control bus 803, and memory data bus 804. In the memory unit 801, the memory cell array is divided into 16 memory blocks. Memory unit 801 contains defective memory cells within memory blocks 805, 806, 807, and 808. The block numbers for these defective blocks are 02h, 04h, 07h, and 08h.
In this embodiment, the highest 4 memory blocks are allocated as replacement blocks. These 4 memory blocks are tested to be functional before placed into service.
The memory access controller 809 performs the control functions for the replacement operation. The memory address decoder 810 decodes the selected memory address bits into 16 memory block selection lines. The memory status unit 811 specifies the status of the 16 memory blocks.
The memory address generator logic unit 812 generates the appropriate replacement memory address for the replacement memory blocks according to the memory status signals.
The memory selection control unit 813 determines whether to select the original memory address or the replacement memory address according to the decoded block selection lines and the memory status signals. The memory address selector 814 performs the final address selection.
FIG. 9 shows a preferred embodiment of a memory access controller for the memory assembly in FIG. 8. In the memory access controller 901, memory address decoder 903 decodes selected memory address bits 902. The memory status unit 904 specifies the status of the memory blocks in the memory unit.
The memory address generator logic unit 905 generates the appropriate replacement memory address 906 for the selected memory block according to the memory status signals.
The memory selection control unit 907 determines whether to select the original memory address or the replacement memory address according to the decoded block selection signals and the memory status signals. Memory address selector 908 performs the final address selection to generate a memory block address 909.
FIG. 10 shows a preferred embodiment of an address generator logic unit for the memory assembly in FIG. 8. The operation of this diagram is similar to FIG. 5. The only difference is that the input location number of the first logic stage is set to hexadecimal value OCh, which is the starting block number of the 4 replacement memory blocks.
The memory status unit 1001 contains the status bits of the 16 memory blocks. The address generator logic block contains 16 basic logic unit stages. The basic logic unit 1002 receives a status bit 1003 from the memory status unit and an input location number 1004 from the previous stage. A logic unit performs a set of basic logic functions to generate am output location number 1006 to the next logic stage. When the corresponding block is selected, the logic unit sends the input location number to the replacement memory address output port 1007.
In this embodiment, the basic logic unit performs a binary increment operation. It receives an input location number from the previous stage. The corresponding status bit input serves as a carry-in bit to the least significant bit (LSB). If the carry-in bit is a zero, the logic unit sends the input location number to the next stage as the output location number. If the carry-in bit is a one, the logic unit increments the input location number by 1 and sends it to the next stage as the output location number.
In FIG. 10, the first logic unit receives the hexadecimal value OCh from the starting address setting 1005 as the input location number. The input-output numbers are marked for each subsequent logic unit as illustrated. The generated memory address outputs for the defective memory blocks 02h, 04h, 07h, and 08h are shown as OCh, ODh, OEh, and OFh respectively. These replacement memory addresses are used instead of the original memory address for the defective memory block locations.
The defective memory block number 02h is replaced with standby memory block OCh. The defective memory block number 04h is replaced with standby memory block ODh. The defective memory block number 07h is replaced with standby memory block OEh. The defective memory block number 08h is replaced with standby memory block OFh. FIG. 11 shows a different preferred embodiment of an address generator unit for the memory assembly in FIG. 8. This operation uses a different basic logic unit stage. Instead of performing an increment operation, the basic logic unit stage performs a decrement operation.
The memory status unit 1101 contains the status bits of the 16 memory blocks. The location identification logic unit contains 16 basic logic unit stages. The basic logic unit 1102 receives a status bit 1103 from the memory status unit and an input location number 1104 from the previous stage. A logic unit performs a set of basic logic functions to generate an output location number 1106 to the next logic stage. When the corresponding block is selected, the logic unit sends the input location number to the replacement memory address output port 1107.
In this embodiment, the basic logic unit performs a binary decrement operation. It receives an input location number from the previous stage. The corresponding status bit input serves as a borrow input to the least significant bit (LSB). If the status bit is a zero, the logic unit sends the input location number to the next stage as the output location number. If the status bit is a one, the logic unit decrements the input location number by 1 and sends it to the next stage as the output location number.
In FIG. 11, the first logic unit receives the hexadecimal value OFh from the starting address setting 1105 as the input location number. The input-output numbers are marked for each subsequent logic unit as illustrated. The generated location numbers for the defective memory blocks 02h, 04h, 07h, and 08h are shown as OFh, OEh, ODh, and OCh respectively. These replacement memory addresses are used instead of the original memory address for the defective memory block locations.
The defective memory block number 02h is replaced with standby memory block OFh. The defective memory block number 04h is replaced with standby memory block OEh. The defective memory block number 07h is replaced with standby memory block ODh. The defective memory block number 08h is replaced with standby memory block OCh.
With this embodiment, regardless of the number of defective blocks, the starting location number input to the first logic stage is always OFh. The location number output of the last logic stage 1108 in this case is OBh, which is the highest logical block address.
FIG. 12 shows a preferred embodiment of a basic logic unit stage in the memory address generator logic unit.
In this embodiment, the basic logic block 1201 contains a 4-bit decrement logic unit stage. The primary memory block status bit 1202 serves as a borrow-in signal. When the borrow-in is 0, the input relocation number 1203 passes through unchanged to the output relocation number port 1204. When the borrow-in is 1, the input relocation number 1203 is decremented by 1 and then sent to the output relocation number port 1204. When the corresponding memory block is selected by the selection signal 1205, the basic logic unit stage sends the input relocation number 1203 through the connection unit 1206 to the replacement memory address output port 1207.
FIG. 13 shows another preferred embodiment of an address generator logic unit for the memory assembly in FIG. 8. In the memory status unit 1301, there are 16 status bits, one bit for each memory block. A functional block is marked with a 0 in the corresponding status entry. A defective block is marked with a 1 in the corresponding status entry.
The address generator logic unit contains 16 basic logic unit stages, one for each memory block status bit. The basic logic unit 1302 receives a status bit 1303 from the memory status unit and an input location number 1304 from the previous stage. A logic unit performs a set of basic logic functions to generate an output location number 1306 to the next logic stage. The logic unit also sends the input location number to the logical memory address output port 1307.
The basic logic unit performs a binary increment operation. It receives an input location number from the previous stage and a status bit from the status unit.
In this embodiment, the status bit input is used in a slightly different way. It is first inverted and then used as a carry-in bit to the least significant bit (LSB). If the status bit is a 1, the carry-in bit is 0 and the logic unit sends the input location number to the next stage as the output location number. If the status bit is a 0, the carry-in bit is 1 , the logic unit increments the input location number by 1 and sends it to the next stage as the output location number. In FIG. 13, the first logic unit receives the hexadecimal value OOh as the input location number 1304 from the starting location number 1305. The input- output numbers are marked for each subsequent logic unit as illustrated. The generated logical memory location numbers for the functional memory blocks OOh, Olh, 03h, 05h, 06h, 09h, OAh, OBh, OCh, ODh, OEh and OFh are shown as OOh, Olh, 02h, 03h, 04h, 05h, 06h, 07h, 08h, 09h, OAh, and OBh respectively.
The location number output of the last logic stage 1308 in this case is OCh, which is the next logical block address after this assembly. It may be used as the starting address number of the next memory controller following this one.
Upon receiving the memory address from the address bus, a basic logic unit compares the input memory address 1309 with the generated logical memory location value 1307 in the comparator 1308. If there is a match, the corresponding location selection line 1310 is set to 1. If there is no match, the corresponding location selection line 1310 is set to 0.
The location address encoder 1311 encodes the location selection lines 1310 from all the functional logic units to generate a final memory address output number 1312.
In responds to memory address inputs OOh, Olh, 02h, 03h, 04h, 05h, 06h, 07h, 08h, 09h, OAh, and OBh, this logic unit will generate the functional block numbers OOh, Olh, 03h, 05h, 06h, 09h, OAh, OBh, OCh, ODh, OEh and OFh respectively. For example, if the memory address input is 07h, the generated memory address will be OBh. FIG. 14 shows a preferred embodiment of a basic logic unit stage for the address generator logic unit in FIG. 13.
The logic operation unit 1401 performs a binary increment operation. It receives an input location number 1403 from the previous stage and a status bit 1402 from the status unit.
In this embodiment, the status bit input is first inverted and then used as a carry-in bit to the least significant bit (LSB). If the status bit is a 1, the carry-in bit is 0 and the logic unit sends the input location number to the next stage as the output location number. If the status bit is a 0, the carry-in bit is 1, the logic unit increments the input location number by 1 and sends it to the next stage as the output location number.
Upon receiving the memory address 1405 from the address bus, a logic comparator 1406 compares the input memory address 1405 with the logical memory location value 1403. If there is a match and the status input is a 0 for a functional unit, the corresponding location selection line 1407 is set to 1. If there is no match, the corresponding location selection line 1407 is set to 0.
FIG. 15 shows another preferred embodiment of an address generator logic unit for the memory assembly in FIG. 8. The operation is similar to that of FIG. 13 except for a different starting address number. The starting address number 1501 is hexadecimal value 02h.
In FIG. 15, the first logic unit receives the starting location number 1501 as the input location number. The input-output numbers are marked for each subsequent logic unit as illustrated. The generated logical memory address numbers for the functional memory blocks OOh, Olh, 03h, 05h, 06h, 09h, OAh, OBh, OCh, ODh, OEh and OFh are shown as 02h, 03h, 04h, 05h, 06h, 07h, 08h, 09h, OAh, OBh, OCh, and ODh respectively.
The location number output of the last logic stage 1502 in this case is OEh, which is the next logical block address after this assembly. It may be used as the starting address number of the next memory controller following this one.
In responds to memory address inputs 02h, 03h, 04h, 05h, 06h, 07h, 08h, 09h, OAh, OBh, OCh, and ODh, this logic unit will generate the functional block numbers OOh, Olh, 03h, 05h, 06h, 09h, OAh, OBh, OCh, ODh, OEh and OFh respectively. For example, if the memory address input is 07h, the generated address will be 09h.
FIG. 16 shows a preferred embodiment of the present invention for a memory module assembly. The first group of memory chips contains four primary memory units 1601. The second group of memory chips contains one standby memory unit 1602. The memory access controller 1603 controls the enabling of these two memory groups. The controller also generates the address for the standby memory unit 1602.
In FIG. 16, the block size of the standby memory unit is smaller than the block size of the primary memory units. The data width of the standby memory unit is also different from the data width of the primary memory units. To perform the replacement under these conditions, the memory data from the standby memory block is routed to the appropriate memory data positions within a primary block addressing space at the appropriate time to replace the defective areas in the primary memory units.
For example, a standby memory block is assigned to replace a memory area within the shaded region in the primary memory unit in FIG.16. The shaded region is eight times the size of the standby memory block. This introduces some constraints on the replacement process.
As illustrated, the standby memory block is designated to replace the marked area 1604 within the shaded region. The selection signal is based on some memory address bits, the physical location of the memory elements, fixed circuit settings, programmable storage cells, or a combination of these parameters.
For example, a sub-block address tag may be attached to each memory status indicator to define the sub-block location of the defective area to be replaced.
FIG. 17 shows a preferred embodiment of the data routing circuit in a memory access controller for the memory assembly in FIG. 16. In this embodiment, the memory data from the standby memory unit is routed to the specified positions for the primary memory units.
Upon control signals, a decoder logic block 1701 decodes two address lines 1702 into data position control lines 1703. These data position control lines enable the memory data 1704 from a standby memory unit through the data output connecting elements 1705 to the memory data output port 1706. As an example, assume that there are thirty-two data bits DO to D31. The decoded line 0 controls data bits DO to D7. Decoded line 1 controls data bits D8 to D15. Decoded line 2 controls data bits D16 to D23. Decoded line 3 controls data bits D24 to D31. If the two address lines are 01, the decoded line 1703 will enable the eight-bit data 1704 from the standby memory unit onto data bits D8 to D15 through the connecting element 1705.
FIG. 18 shows a different preferred embodiment of the present invention for a memory module assembly. The first group of memory chips contains four primary memory units 1801. The second group of memory chips contains one standby memory unit 1802. The memory access controller 1803 controls the enabling of these two memory groups. The controller also generates the address for the standby memory unit 1802.
In FIG. 18, the block size and data width of the standby memory unit are also different from the block size and data width of the primary memory units.
To perform the replacement under these conditions, the memory data from the standby memory block is routed to the appropriate memory data positions within a primary block addressing space at the appropriate time to replace the defective areas in the primary memory units.
As illustrated, the standby memory block is designated to replace the marked area 1804 within the shaded region. The selection signal is based on some memory address bits, the physical location of the memory elements, fixed circuit settings, programmable storage cells, or a combination of these parameters. For example, a sub-block address tag may be attached to each memory status indicator to define the sub-block location of the defective area to be replaced.
To provide more flexibility in the assignment of standby memory block to the appropriate area within a primary block addressing space, the memory access controller 1803 reassigns some of the address bits for the primary memory units.
FIG. 19 shows a preferred embodiment of a memory access controller for the memory assembly in FIG. 18. In this embodiment, the memory data from the standby memory unit is routed to the specified positions for the primary memory units, similar to the operation in FIG.17.
Upon control signals, a decoder decodes two address lines into four data position control lines. These data position control lines enable the memory data from a standby memory unit through the data output connecting elements to the memory data output port.
In addition, there is an address reassignment mechanism 1901 to reassign some of the address bits for the primary memory units.
FIG. 20 shows another different preferred embodiment of the present invention for a memory module assembly. It contains only one group of memory units 2001. The memory access controller 2002 provides an address reassignment mechanism to reassign the address space for the memory units in order to place them in the appropriate memory regions such that the memory module can be used in a degraded manner. In this case, seven of the eight memory regions remain functional after the mapping.

Claims

CLAIMS: I claim:
1. A memory device, chip or module package comprising:
(a) a plurality of package memory data lines;
(b) a plurality of package memory address lines;
(c) a first group of at least one memory sub-packages, each having a plurality of sub-package data lines, a plurality of sub-package address lines, and a plurality of sub-package memory cells partitioned into a plurality of sub-package memory cell blocks each containing at least one memory cells;
(d) a second group of at least one memory sub-packages, each having a plurality of sub-package data lines, a plurality of sub-package address lines, and a plurality of sub-package memory cells partitioned into a plurality of sub-package memory cell blocks each containing at least one memory cells;
(e) a memory access controller, having a memory selection control unit, a plurality of memory status indicators and a plurality of memory address generator logic units; wherein the first group of memory sub-packages contain at least one defective memory sub-package; wherein the memory status indicators state whether a memory location in the first group of sub-packages is functional or defective; wherein the sub-package address lines in the second group are coupled, at least in part, to the outputs of the address generator logic units; wherein the memory selection control unit enables either the first group of memory sub-packages or the second group of memory sub-packages, at the appropriate memory timing cycles, according to the package memory address; wherein a memory address generator logic unit contains a plurality of basic logic unit stages, each stage performing a logic operation such as increment, decrement, addition, subtraction, and, or, exclusive-or, inversion, or a combination of these operations according to the corresponding memory status indicator;
2. The memory package of claim 1, wherein some or all of the memory sub-packages in the second group are embedded within the same device, chip or module subassembly as the memory access controller.
3. The memory package of claim 1, wherein the memory status indicators are a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, or programmable storage cells controlled by internal or external control signals.
4. The memory package of claim 1 , further comprising a data routing unit to route the memory data from the standby memory unit to replace the appropriate bit position and addressing space of the primary memory unit according to a set of parameters which may include selected address bits, physical location of the memory elements, fixed circuit settings, or programmable storage cells controlled by internal or external control signals.
5. A memory device, chip or module package comprising: (a) a plurality of package memory data lines; (b) a plurality of package memory address lines;
(c) a first group of at least one memory sub-packages, each having a plurality of sub-package data lines, a plurality of sub-package address lines, and a plurality of sub-package memory cells partitioned into a plurality of sub-package memory cell blocks each containing at least one memory cells;
(d) a second group of at least one memory sub-packages, each having a plurality of sub-package data lines, a plurality of sub-package address lines, and a plurality of sub-package memory cells partitioned into a plurality of sub-package memory cell blocks each containing at least one memory cells;
(f) a memory access controller, having a memory selection control unit, a plurality of memory status indicators and a plurality of memory address generator logic units; wherein the first group of memory sub-packages contain at least one defective memory sub-package; wherein the memory status indicators state whether a memory location in the first group of sub-packages is functional or defective; wherein the sub-package address lines in the second group are coupled, at least in part, to the outputs of the address generator logic units; wherein the memory selection control unit enables either the first group of memory sub-packages or the second group of memory sub-packages, at the appropriate memory timing cycles, according to the package memory address;
6. The memory package of claim 5, wherein some or all of the memory sub-packages in the second group are embedded within the same device, chip or module subassembly as the memory access controller.
7. The memory package of claim 5, wherein the memory status indicators are a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, or programmable storage cells controlled by internal or external control signals.
8. The memory package of claim 5, further comprising a data routing unit to route the memory data from the standby memory unit to replace the appropriate bit position and addressing space of the primary memory unit according to a set of parameters which may include selected address bits, physical location of the memory elements, fixed circuit settings, or programmable storage cells controlled by internal or external control signals.
9. A memory device, chip or module package comprising:
(a) a plurality of package memory data lines;
(b) a plurality of package memory address lines;
(c) a group of at least one memory sub-packages, each having a plurality of sub- package data lines, a plurality of sub-package address lines, and a plurality of sub-package memory cells partitioned into a plurality of sub-package memory cell blocks each containing at least one memory cells;
(g) a memory access controller, having a plurality of memory status indicators and a plurality of memory address generator logic units; wherein the group of memory sub-packages contain at least one defective memory sub-package; wherein the memory status indicators state whether a memory location in the sub- packages is functional or defective; wherein the sub-package address lines are coupled, at least in part, to the outputs of the address generator logic units; wherein a memory address generator logic unit contains a plurality of basic logic unit stages, each stage performing a logic operation such as increment, decrement, addition, subtraction, and, or, exclusive-or, inversion, or a combination of these operations according to the corresponding memory status indicator;
10. The memory package of claim 9, wherein the memory status indicators are a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, or programmable storage cells controlled by internal or external control signals.
11. The memory package of claim 9, further comprising a data routing unit to route the memory data from the standby memory unit to replace the appropriate bit position and addressing space of the primary memory unit according to a set of parameters which may include selected address bits, physical location of the memory elements, fixed circuit settings, or programmable storage cells controlled by internal or external control signals.
12. A memory device, chip or module package comprising: (a) a plurality of package memory data lines; (b) a plurality of package memory address-control lines;
(c) a group of at least one memory sub-packages, each having a plurality of sub- package data lines, a plurality of sub-package address lines, and a plurality of sub-package memory cells partitioned into a plurality of sub-package memory cell blocks each containing at least one memory cells;
(h) a memory access controller, having a plurality of memory status indicators and a plurality of memory address generator logic units; wherein the group of memory sub-packages contain at least one defective memory sub-package; wherein the memory status indicators state whether a memory location in the sub- packages is functional or defective; wherein the sub-package address lines are coupled, at least in part, to the outputs of the address generator logic units;
13. The memory package of claim 12, wherein the memory status indicators are a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, or programmable storage cells controlled by internal or external control signals.
14. The memory package of claim 12, further comprising a data routing unit to route the memory data from the standby memory unit to replace the appropriate bit position and addressing space of the primary memory unit according to a set of parameters which may include selected address bits, physical location of the memory elements, fixed circuit settings, or programmable storage cells controlled by internal or external control signals.
15. An address generator logic unit comprising:
(a) a plurality of input flags;
(b) a starting location number;
(c) a plurality of basic logic sub-unit stages, one for each input flag; wherein a basic logic sub-unit stage contains a control flag input, an input location number from the previous stage, an output location number to the next stage, and a sub-unit address output. wherein a basic logic sub-unit stage performs a logic operation such as increment, decrement, addition, subtraction, and, or, exclusive-or, inversion, or a combination of these operations according to the control flag input;
16. The address generator logic unit of claim 15, wherein an input flags are a set of fixed or variable settings, which is a set of metal contacts, jumpers, resistors, logic bits, or programmable storage cells controlled by internal or external control signals.
17. The address generator logic unit of claim 15, further comprising a plurality of addressing or selection signal inputs to select a sub-unit address output to send out as a unit address output.
18. The address generator logic unit of claim 15, further comprising an address input, selected bits of said address input either participates in the logic operation of a basic logic sub-unit stage or combine with the sub-unit address outputs to form a unit address output.
PCT/US2001/021511 2000-07-18 2001-07-09 Memory access method and apparatus WO2002006960A1 (en)

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Citations (2)

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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5602987A (en) * 1989-04-13 1997-02-11 Sandisk Corporation Flash EEprom system
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