WO2005022338A3 - Improved computerized extension apparatus and methods - Google Patents

Improved computerized extension apparatus and methods Download PDF

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Publication number
WO2005022338A3
WO2005022338A3 PCT/US2004/027887 US2004027887W WO2005022338A3 WO 2005022338 A3 WO2005022338 A3 WO 2005022338A3 US 2004027887 W US2004027887 W US 2004027887W WO 2005022338 A3 WO2005022338 A3 WO 2005022338A3
Authority
WO
WIPO (PCT)
Prior art keywords
extensions
methods
extension
design
addition
Prior art date
Application number
PCT/US2004/027887
Other languages
French (fr)
Other versions
WO2005022338A2 (en
Inventor
Lee Hewitt
Mark Farr
Chao Dong
Simon Bradley
Original Assignee
Arc Int
Lee Hewitt
Mark Farr
Chao Dong
Simon Bradley
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arc Int, Lee Hewitt, Mark Farr, Chao Dong, Simon Bradley filed Critical Arc Int
Priority to EP04782382A priority Critical patent/EP1668444A4/en
Publication of WO2005022338A2 publication Critical patent/WO2005022338A2/en
Publication of WO2005022338A3 publication Critical patent/WO2005022338A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00Details relating to the type of the circuit
    • G06F2115/08Intellectual property [IP] blocks or IP cores

Abstract

Apparatus and methods for integrated circuit (IC) design (fig 1-14), including the configuration and addition of extensions to the design (fig 1-14). In one exemplary embodiment, a computer program rendered in an object-oriented language implementing the aforementioned methods for automatically adding user-customized extensions to digital processors is disclosed (fig 1-14). The program comprises an extension tool which is adapted for varying levels of abstraction, and to significantly automate the creation and generation of various different extension types including for example ALUs, condition codes, and registers (fig 1-14). A markup language (e.g., XML) database of abstracted extension components is utilized to permit ready addition and modification of extensions, as well as applicability of the extensions across different target architectures (fig 1-14).
PCT/US2004/027887 2003-08-29 2004-08-27 Improved computerized extension apparatus and methods WO2005022338A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04782382A EP1668444A4 (en) 2003-08-29 2004-08-27 Improved computerized extension apparatus and methods

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/651,560 US20050049843A1 (en) 2003-08-29 2003-08-29 Computerized extension apparatus and methods
US10/651,560 2003-08-29

Publications (2)

Publication Number Publication Date
WO2005022338A2 WO2005022338A2 (en) 2005-03-10
WO2005022338A3 true WO2005022338A3 (en) 2006-12-28

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PCT/US2004/027887 WO2005022338A2 (en) 2003-08-29 2004-08-27 Improved computerized extension apparatus and methods

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US (1) US20050049843A1 (en)
EP (1) EP1668444A4 (en)
KR (1) KR20060087537A (en)
CN (1) CN1973290A (en)
WO (1) WO2005022338A2 (en)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1692558A2 (en) 2003-12-01 2006-08-23 CDM Optics, Inc. System and method for optimizing optical and digital system designs
US7944467B2 (en) * 2003-12-01 2011-05-17 Omnivision Technologies, Inc. Task-based imaging systems
US7788078B1 (en) * 2004-02-27 2010-08-31 Synopsys, Inc. Processor/memory co-exploration at multiple abstraction levels
US7415701B2 (en) * 2005-02-17 2008-08-19 Intel Corporation Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine
US7634768B2 (en) * 2005-02-17 2009-12-15 Intel Corporation Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machine
US7363610B2 (en) * 2005-06-21 2008-04-22 Nvidia Corporation Building integrated circuits using a common database
EP1736905A3 (en) * 2005-06-21 2007-09-05 Nvidia Corporation Building integrated circuits using logical units
US7483823B2 (en) 2005-06-21 2009-01-27 Nvidia Corporation Building integrated circuits using logical units
CN102147853B (en) * 2005-09-19 2013-01-09 全视技术有限公司 Image outputting method for generating scene
US7793248B1 (en) * 2005-11-23 2010-09-07 Altera Corporation Method and apparatus for parameterizing hardware description language code in a system level design environment
US20070162593A1 (en) * 2006-01-09 2007-07-12 Microsoft Corporation Abstracting help calls using a documentation abstraction layer
US7757224B2 (en) * 2006-02-02 2010-07-13 Microsoft Corporation Software support for dynamically extensible processors
US9064076B1 (en) * 2006-03-23 2015-06-23 Synopsys, Inc. User interface for facilitation of high level generation of processor extensions
US7827517B1 (en) * 2006-05-19 2010-11-02 Altera Corporation Automated register definition, builder and integration framework
US9158538B2 (en) * 2007-05-21 2015-10-13 International Business Machines Corporation User-extensible rule-based source code modification
KR100911324B1 (en) * 2007-06-22 2009-08-07 삼성전자주식회사 Method for managing variability point and appratus therefor
US8122428B2 (en) 2007-06-26 2012-02-21 Analog Devices, Inc. Methods and apparatus for automation and facilitating design of register maps
US8326592B2 (en) * 2007-12-21 2012-12-04 Cadence Design Systems, Inc. Method and system for verifying electronic designs having software components
WO2010064205A1 (en) * 2008-12-03 2010-06-10 Nxp B.V. System and method for viterbi decoding using application specific extensions
KR101553652B1 (en) * 2009-02-18 2015-09-16 삼성전자 주식회사 Apparatus and method for compiling instruction for heterogeneous processor
WO2011123151A1 (en) * 2010-04-02 2011-10-06 Tabula Inc. System and method for reducing reconfiguration power usage
US20110307904A1 (en) * 2010-06-14 2011-12-15 James Malnati Method and apparatus for automation language extension
US20120185820A1 (en) * 2011-01-19 2012-07-19 Suresh Kadiyala Tool generator
US9480077B2 (en) 2011-06-06 2016-10-25 Telefonaktiebolaget Lm Ericsson (Publ) Methods and systems for a generic multi-radio access technology
US9043765B2 (en) * 2011-11-09 2015-05-26 Microsoft Technology Licensing, Llc Simultaneously targeting multiple homogeneous and heterogeneous runtime environments
US8650525B2 (en) * 2012-06-22 2014-02-11 Altera Corporation Integrated circuit compilation
US9880820B2 (en) * 2013-06-02 2018-01-30 Microsoft Technology Licensing, Llc Programming language with extensions using dynamic keywords
US9875290B2 (en) * 2014-08-15 2018-01-23 Deloitte It Inc. Method, system and computer program product for using an intermediation function
US9507891B1 (en) * 2015-05-29 2016-11-29 International Business Machines Corporation Automating a microarchitecture design exploration environment
US11275582B2 (en) * 2017-01-06 2022-03-15 Montana Systems Inc. Event-driven design simulation
CN108460179A (en) * 2018-01-11 2018-08-28 郑州云海信息技术有限公司 Belong to the method and system of line in pcb board design using quick key switch GND
WO2022182796A1 (en) * 2021-02-23 2022-09-01 Coda Project, Inc. System, method, and apparatus for publication and external interfacing for a unified document surface

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020156929A1 (en) * 2001-04-23 2002-10-24 International Business Machines Corporation XML-based system and method for collaborative web-based design and verification of system-on-a-chip
US20030009658A1 (en) * 2001-06-16 2003-01-09 Chen Michael Y. Self-describing IP package for enhanced platform based SOC design

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4763242A (en) * 1985-10-23 1988-08-09 Hewlett-Packard Company Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility
US5535331A (en) * 1987-09-04 1996-07-09 Texas Instruments Incorporated Processor condition sensing circuits, systems and methods
US5555201A (en) * 1990-04-06 1996-09-10 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US5544067A (en) * 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
US5867399A (en) * 1990-04-06 1999-02-02 Lsi Logic Corporation System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description
US5553002A (en) * 1990-04-06 1996-09-03 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface
US5450586A (en) * 1991-08-14 1995-09-12 Hewlett-Packard Company System for analyzing and debugging embedded software through dynamic and interactive use of code markers
US5491640A (en) * 1992-05-01 1996-02-13 Vlsi Technology, Inc. Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication
EP0592715B1 (en) * 1992-10-15 1997-06-11 Siemens Aktiengesellschaft Checking design for testability rules with a VHDL simulator
US5361373A (en) * 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5404319A (en) * 1993-02-11 1995-04-04 Analog, Inc. Translation of behavioral modeling properties into an analog hardware description language
US5493508A (en) * 1994-06-01 1996-02-20 Lsi Logic Corporation Specification and design of complex digital systems
US5537580A (en) * 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US6026219A (en) * 1995-05-12 2000-02-15 Synopsys, Inc. Behavioral synthesis links to logic synthesis
US5898595A (en) * 1995-05-26 1999-04-27 Lsi Logic Corporation Automated generation of megacells in an integrated circuit design system
US5841663A (en) * 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
US5870588A (en) * 1995-10-23 1999-02-09 Interuniversitair Micro-Elektronica Centrum(Imec Vzw) Design environment and a design method for hardware/software co-design
US5696956A (en) * 1995-11-08 1997-12-09 Digital Equipment Corporation Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents
US5819064A (en) * 1995-11-08 1998-10-06 President And Fellows Of Harvard College Hardware extraction technique for programmable reduced instruction set computers
US6035123A (en) * 1995-11-08 2000-03-07 Digital Equipment Corporation Determining hardware complexity of software operations
US5819050A (en) * 1996-02-29 1998-10-06 The Foxboro Company Automatically configurable multi-purpose distributed control processor card for an industrial control system
US5854929A (en) * 1996-03-08 1998-12-29 Interuniversitair Micro-Elektronica Centrum (Imec Vzw) Method of generating code for programmable processors, code generator and application thereof
US6173434B1 (en) * 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US5748875A (en) * 1996-06-12 1998-05-05 Simpod, Inc. Digital logic simulation/emulation system
US5812416A (en) * 1996-07-18 1998-09-22 Lsi Logic Corporation Integrated circuit design decomposition
US5994892A (en) * 1996-07-31 1999-11-30 Sacramento Municipal Utility District Integrated circuit design automatic utility meter: apparatus & method
JPH10222374A (en) * 1996-10-28 1998-08-21 Altera Corp Method for providing remote software technological support
US6006022A (en) * 1996-11-15 1999-12-21 Microsystem Synthesis, Inc. Cross-linked development and deployment apparatus and method
US5854930A (en) * 1996-12-30 1998-12-29 Mci Communications Corporations System, method, and computer program product for script processing
US6772136B2 (en) * 1997-08-21 2004-08-03 Elaine Kant System and method for financial instrument modeling and using Monte Carlo simulation
US6195593B1 (en) * 1997-09-03 2001-02-27 Seiko Epson Corporation Reusable modules for complex integrated circuit devices
US6226776B1 (en) * 1997-09-16 2001-05-01 Synetry Corporation System for converting hardware designs in high-level programming language to hardware implementations
US6009251A (en) * 1997-09-30 1999-12-28 Synopsys, Inc. Method and system for layout verification of an integrated circuit design with reusable subdesigns
US6360350B1 (en) * 1997-10-07 2002-03-19 International Business Corporation Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms
US5999734A (en) * 1997-10-21 1999-12-07 Ftl Systems, Inc. Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models
US5949993A (en) * 1997-10-31 1999-09-07 Production Languages Corporation Method for the generation of ISA simulators and assemblers from a machine description
EP0926589A1 (en) * 1997-12-24 1999-06-30 STMicroelectronics S.r.l. Processor having internal control instructions
US6421818B1 (en) * 1998-02-20 2002-07-16 Lsi Logic Corporation Efficient top-down characterization method
US6378123B1 (en) * 1998-02-20 2002-04-23 Lsi Logic Corporation Method of handling macro components in circuit design synthesis
US6438678B1 (en) * 1998-06-15 2002-08-20 Cisco Technology, Inc. Apparatus and method for operating on data in a data communications system
CA2345648A1 (en) * 1998-09-30 2000-04-06 Cadence Design Systems, Inc. Block based design methodology
US6862563B1 (en) * 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
EP1121656A2 (en) * 1998-10-14 2001-08-08 Arc Cores Limited Method and apparatus for managing the configuration and functionality of a semiconductor design
US6356796B1 (en) * 1998-12-17 2002-03-12 Antrim Design Systems, Inc. Language controlled design flow for electronic circuits
US6477697B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set
US6477683B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6385757B1 (en) * 1999-08-20 2002-05-07 Hewlett-Packard Company Auto design of VLIW processors
US6408428B1 (en) * 1999-08-20 2002-06-18 Hewlett-Packard Company Automated design of processor systems using feedback from internal measurements of candidate systems
US6457173B1 (en) * 1999-08-20 2002-09-24 Hewlett-Packard Company Automatic design of VLIW instruction formats
US7089278B1 (en) * 1999-09-07 2006-08-08 Fuji Xerox Co., Ltd. Anchored conversations: adhesive, in-context, virtual discussion forums
WO2001033334A1 (en) * 1999-10-29 2001-05-10 Antrim Design Systems, Inc. Mixed signal synthesis behavioral models and use in circuit design optimization
US20020087828A1 (en) * 2000-12-28 2002-07-04 International Business Machines Corporation Symmetric multiprocessing (SMP) system with fully-interconnected heterogenous microprocessors
US20030009730A1 (en) * 2001-06-16 2003-01-09 Chen Michael Y. Enhanced platform based SOC design including exended peripheral selection and automated IP customization facilitation
KR100818826B1 (en) * 2002-04-25 2008-04-01 에이알씨 인터내셔널 A computerized apparatus for generating a design of an integrated circuit and a method for generating a hierarchy within an integrated circuit design having a plurality of components

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020156929A1 (en) * 2001-04-23 2002-10-24 International Business Machines Corporation XML-based system and method for collaborative web-based design and verification of system-on-a-chip
US20030009658A1 (en) * 2001-06-16 2003-01-09 Chen Michael Y. Self-describing IP package for enhanced platform based SOC design

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1668444A4 *

Also Published As

Publication number Publication date
WO2005022338A2 (en) 2005-03-10
EP1668444A4 (en) 2007-08-01
CN1973290A (en) 2007-05-30
EP1668444A2 (en) 2006-06-14
KR20060087537A (en) 2006-08-02
US20050049843A1 (en) 2005-03-03

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